The present invention relates generally to integrated circuit devices and more particularly to sigma delta modulators, digital to analog converters, and fabrication methods therefore.
Analog to digital (A/D) converters are electrical circuit devices that convert continuous signals, such as voltages or currents, from the analog domain to the digital domain, in which the signals are represented by numbers. A variety of A/D converter types exist, including flash A/Ds, sub-ranging A/Ds, successive approximation A/Ds, and integrating A/Ds. Another type of A/D converter is known as a delta sigma or sigma delta (e.g., S-D) A/D, which may sample an analog signal at a very high sampling rate (oversampling) in order to perform a noise shaping function. The oversampling is commonly performed at a multiple of the Nyquist rate (Fs) for a given input signal frequency content (e.g., oversampling at 10 to 1000 times Fs), wherein quantization noise power is spread over a bandwidth equal to the sampling frequency. Digital filtering is then employed on the digital output to achieve a high resolution. Decimation may then be employed to reduce the effective sampling rate back to the xe2x80x9cNyquistxe2x80x9d rate.
Sigma delta A/D converters are noise shaping modulators and may be first order, second order, or jth order, where j is a positive integer. For example, a typical first order sigma delta modulator comprises a filter, such as an integrator circuit, which receives the analog input signal as well as a feedback signal, and a quantizer, such as a flash AND converter, which quantizes the filter output signal to create a digital output. In the simplest form, the quantizer may be a single bit A/D, such as a comparator circuit. A digital to analog (D/A) converter creates an analog representation of the current digital output and provides this as the feedback signal to the filter. Multiple order sigma delta modulators may include a series of n filters in the forward path, each filtering the output of the previous filter and receiving an analog feedback signal based on the digitized output of the modulator, where the first filter operates on the input signal to be converted and the feedback signal.
Multi-bit or multi-level sigma delta modulators provide multi-bit digital or quantized outputs, wherein the analog to digital converter thereof is multi-bit. For example, a multi-level flash or other type A/D circuit may receive the output of the final filter and provide a multi-bit digital output representative thereof, wherein the D/A feedback converter is accordingly multi-bit as well. Whereas single-bit sigma delta modulators can achieve good linearity, performance and stability are generally not as good as in multi-bit sigma delta modulators. On the other hand, the harmonic distortion of the sigma delta modulator suffers as more bits are used in the quantizer and D/A circuits. In this regard, the linearity of the multi-bit system is essentially limited by the linearity of the D/A converter, particularly nonlinearity due to mismatch of D/A internal components.
One approach to reducing the adverse effects of D/A component mismatch in multi-bit sigma delta modulators is the use of dynamic element matching (DEM) techniques in the feedback. For instance, DEM systems may be employed in the modulator feedback path to vary the selection of mismatched components in the D/A converter in response to the quantized digital output signal. Such DEM techniques have been employed successfully to reduce the linearity problems in multi-bit sigma delta modulators.
Another performance measure in sigma delta modulators is the production of unintended tone components in the output, sometimes referred to as idle channel tones. This problem is particularly troublesome for static (e.g., DC) or slowly changing input signals, wherein the modulator creates a repetitive pattern, which appears as a tonal component in the output spectrum. To combat this phenomenon, a dither signal is sometimes applied to the input of the quantizer A/D in the modulator, as illustrated in U.S. Pat. No. 6,326,911, assigned to the assignee of the current invention. With respect to idle channel tones, the randomizing effect of certain DEM systems and algorithms may operate to reduce or reject the unwanted tones. However, conventional sigma delta modulators with dynamic element matching for selection of D/A converter components do not provide complete or significant rejection of tones in the case of very slow or DC input signals. Thus, there is a need for improved sigma delta modulators, digital to analog converters, and fabrication methods therefor, by which the undesired tonal components may be reduced in such multi-bit sigma delta modulators.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention relates to sigma delta modulators, digital to analog (D/A) converters, and fabrication methods therefore, by which the undesired tonal components may be mitigated in multi-bit sigma delta modulators employing dynamic element matching, through provision of intentional component mismatch in feedback D/A converters.
In one aspect of the invention, a sigma delta modulator is provided, comprising a filter, a quantizer, a digital to analog converter, and a dynamic element matching (DEM) system. The filter receives an input signal and an analog feedback signal, and provides a filtered output signal. The quantizer receives the filtered output signal and provides a quantized output signal according to the filtered output signal, wherein the quantized output signal corresponds to the input signal. The D/A converter comprises a plurality of circuit elements, individually having an associated element value, where the D/A converter provides the analog feedback signal corresponding to the quantized output signal using circuit elements selected according to the quantized output signal.
The plurality of D/A circuit elements comprise one or more mismatched components or circuit elements as well as a plurality of matched circuit elements, which may be capacitors, resistors, transistors, or any type of component or groups thereof. The mismatched circuit element has a mismatched element value, differing from a design element value by a mismatch amount, and the matched circuit elements have element values within a tolerance amount of the design element value, where the mismatch amount is greater than the tolerance amount. The element values may be any value affecting D/A conversion, such as capacitance, resistance, transistor size, gain, etc. The DEM system operates to vary the selection of circuit elements of the digital to analog converter. The employment of the mismatched circuit element provides or ensures some amount of D/A component mismatch across matching tolerance variation in the manufacture of large numbers of semiconductor devices. As a result, most if not all such manufactured parts will have enough D/A circuit element mismatch to allow the DEM system to reduce or mitigate unwanted idle channel tones in the sigma delta modulator.
Another aspect of the invention provides a D/A converter for providing an analog feedback signal corresponding to a quantized output signal in a sigma delta modulator. The D/A comprises a plurality of circuit elements, individually having an associated element value, where the plurality of circuit elements comprises at least one mismatched circuit element having a mismatched element value differing from a design element value by a mismatch amount, and a plurality of matched circuit elements having element values within a tolerance amount of the design element value, and where the mismatch amount is greater than the tolerance amount.
Yet another aspect of the invention provides a method of fabricating a digital to analog converter for providing an analog feedback signal corresponding to a quantized output signal using a group of circuit elements selected according to the quantized output signal in a sigma delta modulator. The method comprises providing a plurality of matched circuit elements in the group, where the matched circuit elements have element values within a tolerance amount of a design element value. The method further comprises providing at least one mismatched circuit element in the group, which has a mismatched element value differing from the design element value by a mismatch amount, with the mismatch amount being greater than the tolerance amount.
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.